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as1154 dual lvds driver www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 1 - 16 datasheet 1 general description the as1154 is a dual flow-through lvds (low-voltage differential signaling) line driver which accepts and converts lvttl/lvcmos input levels into lvds output signals. the device is perfect for low- power low-noise applications requiring high signaling rates and reduced emi emissions. the device is guaranteed to transmit data at speeds up to 800mbps (400mhz) over controlled impedance media of approximately 100 . supported transmission media are pcb traces, backplanes, and cables. outputs conform to the ansi tia/eia-644 lvds standards. flow- through pinout simplifies pc board layout and reduces crosstalk by separating the lvttl/lvcmos inputs and lvds outputs. the as1154 operates from a single +3.3v supply and is specified for operation from -40c to +85c. figure 1. as1154 - block diagram 2 key features ? flow-through pinout ? guaranteed 800mbps data rate ? 250ps pulse skew (max) ? conforms to ansi tia/eia-644 lvds standards ? single +3.3v supply ? operating temperature range: -40c to +85c ? 8-pin soic package 3 applications digital copiers, laser printers, cellular phone base stations, add/ drop muxes, digital cross-connec ts, dslams, network switches/ routers, backplane interconnect, clock distribution computers, intelligent instruments, controllers, critical microprocessors and microcontrollers, power monitoring, and portable/battery-powered equipment. as1154 vcc in1 in2 gnd out1- out1+ out2+ out2- tx tx
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 2 - 16 as1154 datasheet - pinout 4 pinout pin assignments figure 2. pin assignments (top view) pin descriptions table 1. pin descriptions pin number pin name description 1vcc power supply input. bypass v cc to gnd with 0.1f and 0.001f ceramic capacitors. 2in1 lvttl/lvcmos driver input 3in2 lvttl/lvcmos driver input 4gnd ground 5out2- inverting lvds driver output 6out2+ noninverting lvds driver output 7out1+ noninverting lvds driver output 8out1- inverting lvds driver output out1- out1+ out2+ out2- vcc in1 in2 gnd as1154 1 2 3 4 8 7 6 5
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 3 - 16 as1154 datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not imp lied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings parameter min max units comments electrical parameters vcc to gnd -0.3 5.0 v inx to gnd -0.3 vcc + 0.3 v outx+, outx- to gnd -0.3 5.0 v short circuit duration (outx+, outx-) continuous electrostatic discharge electrostatic discharge hbm +/- 4 kv norm: mil 883 e method 3015, inx, outx+, outx- continous power dissipation (t a = +70c) continous power dissipation 755 mw p t 1 for 8-pin soic package 1. depending on actual pcb layout and pcb used. continous power dissipation derating factor 9.4 mw / c p derate 2 2. p derate derating factor changes the total continuous power dissipation (p t ) if the ambient temperature is not 70oc. therefore for e.g. t a =85oc calculate p t at 85oc = p t - p derate x (85oc - 70oc) temperature ranges and storage conditions junction temperature +150 oc storage temperature range -55 +125 oc package body temperature +260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/ jedec j-std-020?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). humidity non-condensing 5 85 % moisture sensitive level 1 represents a max. floor life time of unlimited
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 4 - 16 as1154 datasheet - electrical characteristics 6 electrical characteristics dc electrical characteristics v cc = +3.0v to +3.6v, t a = -40c to +85c, r l = 100 1%, ( typical values are at v cc = +3.3v, t a = +25c) unless otherwise specified ; 1 notes: 1. currents into the device are positive, and current out of the device is negative. all voltages are referenced to ground exc ept v od . 2. guaranteed by correlation data. 3. all limits are guaranteed. the parameters with min and max va lues are guaranteed with production tests or sqc (statistical quality control) methods. table 3. dc electrical characteristics parameter symbol conditions min typ max unit operating temperature range t a -40 +85 c lvds output (out x +, out x -) differential output voltage v od figure 21 on page 12 250 355 450 mv change in magnitude of v od between complementary output states v od figure 21 on page 12 1 35 mv offset voltage v os figure 21 on page 12 1.125 1.25 1.375 v change in magnitude of v os between complementary output states v os figure 21 on page 12 4 25 mv output high voltage v oh 1.6 v output low voltage v ol 0.90 v differential output short-circuit current 2 i osd v od = 0v -9 ma output short-circuit current i os out x + = 0v at in x = v cc or out x - = 0v at in x = 0v -3.7 -9 ma power-off output current i off v cc = 0v or open, out x + = 0v or 3.6v out x - = 0v or 3.6v, r l = -20 20 a inputs (inx) high-level input voltage v ih 2.0 v cc v low-level input voltage v il gnd 0.8 v input current i in in x = 0v or v cc -20 20 a supply current no-load supply current i cc r l = , in x = v cc or 0v for all channels 2 3.5 ma loaded supply current i ccl r l = 100 , in x = v cc or 0v for all channels 5.5 7.5 ma r l = 100 , in x = v cc or 0v for all channels 8.5 12 ma
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 5 - 16 as1154 datasheet - electrical characteristics switching characteristics v cc = +3.0v to +3.6v, r l = 100 1%, c l = 2.5pf (differential), t a = -40c to +85c, (typical values are at v cc = +3.3v, t a = +25oc) unless otherwise specified ; 1, 2, 3, 10 notes: 1. parameters are guaranteed by design and characterization. 2. c l includes probe and jig capacitance. 3. signal generator conditions for dynamic tests: v ol = 0, v oh = 2.4v, f = 100mhz, 50% duty cycle, ro = 50 , t r 1ns, t f 1ns (0 to 100%). 4. t skd1 is the magnitude difference of differential propagation delay. t skd1 = |t phld - t plhd |. 5. t skd2 is the magnitude difference of t phld or t plhd of one channel to the t phld or t plhd of another channel on the same device. 6. t skd3 is the magnitude difference of any differential propagation delays between devices at the same v cc and within 5c of each other. 7. t skd4 is the magnitude difference of any differential propagation delays between devices operating over the rated supply and tempera - ture ranges. 8. f max signal generator conditions: v ol = 0, v oh = 2.4v, 50% duty cycle, ro = 50 , t r 1ns, t f 1ns (0 to 100%). 9. transmitter output criteria: duty cycle = 45 to 55%, v od 3 250mv. 10. for optimum performance matched circuits should be used. table 4. switching characteristics parameter symbol conditions min typ max unit differential propagation delay, high-to-low t phld figure 20 on page 11 and figure 21 on page 12 1.1 1.268 1.5 ns differential propagation delay, low-to-high t plhd figure 20 on page 11 and figure 21 on page 12 1.1 1.267 1.5 ns differential pulse skew 4 t skd1 figure 20 on page 11 and figure 21 on page 12 90 200 ps differential channel-to-channel skew 5 t skd2 figure 20 on page 11 and figure 21 on page 12 110 250 ps differential part-to-part skew 6 t skd3 figure 20 on page 11 and figure 21 on page 12 750 ps differential part-to-part skew 7 t skd4 figure 20 on page 11 and figure 21 on page 12 900 ps rise time t tlh figure 20 on page 11 and figure 21 on page 12 200 356 800 ps fall time t thl figure 20 on page 11 and figure 21 on page 12 200 352 800 ps maximum operating frequency 8, 9 f max 400 mhz
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 6 - 16 as1154 datasheet - typical operating characteristics 7 typical operating characteristics v cc = +3.3v, c load = 2.5pf (differential), freq = 20mhz, tamb = +25oc, unless otherwise specified ; figure 3. transition time vs. v cc figure 4. transition time vs. temperature figure 5. differential pulse skew vs. v cc figure 6. pulse skew vs. temperature figure 7. differential propagation delay vs. v cc ; figure 8. differential propagation delay vs. temp. 0 50 100 150 200 250 300 350 -50 -30 -10 10 30 50 70 90 ambient temperature(c) transition time (ps) . 230 240 250 260 270 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) transition time (ps) . t tlh t thl t tlh t thl 0 5 10 15 20 25 30 35 -50-30-101030507090 ambient temperature(c) pulse skew (ps) . 0 10 20 30 40 50 60 70 80 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) differential pulse skew (ps) . 0.95 0.97 0.99 1.01 1.03 1.05 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) diff. propagation delay (ns) . t plhd t phld 0.98 1 1.02 1.04 1.06 1.08 1.1 1.12 1.14 -50 -30 -10 10 30 50 70 90 ambient temperature(c) diff. propagation delay (ns) . t plhd t phld
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 7 - 16 as1154 datasheet - typical operating characteristics figure 9. differential output voltage vs. v cc figure 10. differential output voltage vs. frequency figure 11. offset voltage vs. v cc figure 12. offset voltage vs. frequency figure 13. output voltage vs. v cc ; figure 14. output voltage vs. load resistance; 325 330 335 340 345 350 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) differential output voltage (mv) . 0 50 100 150 200 250 300 350 0 50 100 150 200 250 300 350 400 frequency (mhz) differential output voltage (mv) . 1.1 1.15 1.2 1.25 1.3 1.35 0 50 100 150 200 250 frequency (mhz) offset voltage (v) . 1.2 1.21 1.22 1.23 1.24 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) offset voltage (v) . 0.95 1.05 1.15 1.25 1.35 1.45 80 90 100 110 120 130 140 150 load resistance ( ) output voltage (v) . 0.95 1.05 1.15 1.25 1.35 1.45 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) output voltage (v) . v out+ v out- v out+ v out-
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 8 - 16 as1154 datasheet - typical operating characteristics figure 15. i cc vs. v cc figure 16. i cc vs. temperature; figure 17. short circuit current vs. v cc figure 18. i cc vs. frequency 8 9 10 11 12 13 -50-30-101030507090 ambient temperature(c) supply current (ma) . 9 9.4 9.8 10.2 10.6 11 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage (v) supply current (ma) . freq = 100mhz freq = 20mhz 0 2 4 6 8 10 12 14 16 18 0 50 100 150 200 250 frequency (mhz) supply current (ma) . 3.6 3.65 3.7 3.75 3.8 3.85 3.9 3 3.1 3.2 3.3 3.4 3.5 3.6 supply voltage(v) output short circuit current (ma) .
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 9 - 16 as1154 datasheet - detailed description 8 detailed description lvds interface the lvds interface standard is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ansi/tia/eia-644 and ieee 1596.3 standards. the lvds standard uses a lower voltage swing than other common communication stan- dards, achieving higher data rates with reduced power consumption while reducing emi emissions and system susceptibility to noi se. the as1154 is an 800mbps dual differential lvds driver that is designed for high-speed, point-to-point, low-power applications. this device accepts lvttl/lvcmos input levels and translates them to lvds output signals. the as1154 generates a 2.5ma to 4.5ma output current using a current-steering configuration. this current steering approach ind uces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. the driver outputs are short-c ircuit cur- rent limited, and enter a high-impedance state when the device is not powered or is disabled. the current-steering architecture of the as1154 requires a resistive load to terminate the signal and complete the transmission loop. because the device switches current and not voltage, the actual output voltage swing is determined by the value of the termination resi stor at the input of an lvds receiver (as1157, as1158). logic states are determined by the direction of current flow through the termination resisto r. with a typical 3.7ma output current, the as1154 produces an output voltage of 370mv when driving a 100 load. termination because the as1154 is a current-steering device, no output voltage will be generated without a termination resistor. the termin ation resistors should match the differential impedance of the transmission line. output voltage levels depend upon the value of the terminatio n resistor. the as1154 is optimized for point-to-point interface with 100 termination resistors at the receiver inputs. termination resistance values may range between 90 and132 , depending on the characteristic impedance of the transmission medium.
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 10 - 16 as1154 datasheet - applications 9 applications figure 19. typical application circuit power-supply bypassing to bypass v cc , use high-frequency surface-mount ceramic 0.1f and 0.001f capacitors in parallel as close to the device as possible, with th e smaller valued capacitor closest to pin v cc . differential traces input trace characteristics can adversely affect the performance of the as1154. ? use controlled-impedance pc board traces to match the cable characteristic impedance. the termination resistor is also matched to this characteristic impedance. ? eliminate reflections and ensure that noise couples as common mode by running the differential traces near each other. ? reduce skew by using matched trace lengths. tight skew control is required to minimize emissions and proper data recovery of th e devices. ? route each channel?s differential signals very close to each other for optimal cancellation of their respective external magnet ic fields. use a constant distance between the differential traces to avoid irregularities in differential impedance. ? avoid 90 turns (use two 45 turns). ? minimize the number of vias to further prevent impedance irregularities. table 5. function table input output in x out x + out x - ll h h hl 0.8v < v inx < 2.0v undetermined undetermined lvds signals 107 lvttl/lvcmos data inputs lvttl/lvcmos data outputs 100 shielded twisted cable or microstrip pc board traces tx rx as1157 lvds receiver as1154 0.1f 0.001f +3.3v 0.1f 0.001f +3.3v
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 11 - 16 as1154 datasheet - applications cables and connectors supported transmission media include printed circuit board traces, backplanes, and cables. ? use cables and connectors with matched differential impedance (typically 100 ) to minimize impedance mismatches. ? balanced cables such as twisted pair offer superior signal quality and tend to generate less emi due to magnetic field cancelin g effects. bal- anced cables pick up noise as common mode, which is rejected by the lvds receiver. ? avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable. board layout the device should be placed as close to the interface connector as possible to minimize lvds trace length. ? keep the lvds and any other digital signals separated from each other to reduce crosstalk. ? use a four-layer pc board that provides separate power, ground, lvds signals, and input signals. ? isolate the input lvds signals from each other and the output lvcmos/lvttl signals from each other to prevent coupling. ? separate the input lvds signals from the output signals planes with the power and ground planes for best results. figure 20. driver propagation delay and transition time waveforms t thl t tlh t plhd t phld 0 differential 1.5v 20% 80% 0 20% out x- out x+ in x v oh v ol 0 1.5v v diff = (v out x + ) - (v out x - ) 80% 0 0
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 12 - 16 as1154 datasheet - applications figure 21. driver propagation delay and transition time test circuit figure 22. driver v od and v os te s t c i r c u i t out x- generator 50 c l r l out x+ v os v od out x+ out x- r l /2 r l /2 v cc gnd in x
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 13 - 16 as1154 datasheet - package drawings and markings 10 package drawin gs and markings figure 23. 8-pin soic marking table 6. packaging code aywwrzz yy ww r zz last two digits of the current year manufacturing week plant identifier free choice / traceability code
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 14 - 16 as1154 datasheet - package drawings and markings figure 24. 8-pin soic package
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 15 - 16 as1154 datasheet - ordering information 11 ordering information the devices are available as the standard products shown in table 7. note: all products are rohs compliant. buy our products or get free samples online at icdirect: http://www.austriamicr osystems.com/icdirect technical support is found at http://www.austriamicrosystems.com/technical-support for further information and requests, please contact us mailto:sales@austriamicrosystems.com or find your local distributor at http://www.austriamicros ystems.com/distributo table 7. ordering information ordering code marking description delivery form package as1154-bsou as1154 dual lvds driver tubes 8-pin soic as1154-bsot as1154 dual lvds driver tape and reel 8-pin soic
www.austriamicrosystems.com/interfaces-lvds/as1154 revision 1.02 16 - 16 as1154 datasheet copyrights copyright ? 1997-2010, austriamicrosystems ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registe red ?. all rights reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by austriamicrosystems ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. austriamicrosystems ag makes no warranty, express, statutory, implied, or by description regarding the information set forth he rein or regarding the freedom of the described devices from patent infringement. austriamicrosystems ag reserves the right to change specificatio ns and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with austriamic rosystems ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temper ature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems ag for each application. for shipments of les s than 100 parts the manufacturing flow might show deviations from the st andard production flow, such as test flow or test location. the information furnished here by austriamicrosystems ag is believed to be correct and accurate. however, austriamicrosystems ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems ag rendering of technical or other services. contact information headquarters austriamicrosystems ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel: +43 (0) 3136 500 0 fax: +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.austriamicrosystems.com/contact

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